The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2023

Filed:

Feb. 24, 2022
Applicant:

Seagate Technology Llc, Fremont, CA (US);

Inventors:

Bharat Londhe, Pune, IN;

Deep Neema, Pune, IN;

Komal Shah, Mumbai, IN;

Assignee:

SEAGATE TECHNOLOGY LLC, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3177 (2006.01); G01R 31/3183 (2006.01); G01R 31/3185 (2006.01); G01R 31/3181 (2006.01); G01R 31/319 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/3181 (2013.01); G01R 31/31921 (2013.01); G01R 31/318307 (2013.01); G01R 31/318335 (2013.01); G01R 31/318533 (2013.01); G01R 31/318544 (2013.01); G01R 31/318547 (2013.01);
Abstract

A method includes injecting scan patterns into an input of a decompressor that distributes the scan patterns to a plurality of scan chains whose outputs are coupled to inputs of a compressor, which provides a compressed scan test result representing the plurality of scan chains. The method also includes, in response to the compressed scan test result being indicative of failure, identifying a particular scan chain of the plurality of scan chains that is responsible for the failure by a debug circuit that is coupled to the input of the decompressor and to a compressor output. The debug circuit enables an output of any single scan chain of the plurality of scan chains to be available at the compressor output while suppressing outputs of all other scan chains of the plurality of scan chains.


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