The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2023
Filed:
Sep. 24, 2021
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Dexin Kong, Redmond, WA (US);
Ashim Dutta, Clifton Park, NY (US);
Ekmini Anuja De Silva, Slingerlands, NY (US);
Daniel Schmidt, Niskayuna, NY (US);
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H10N 70/00 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01);
U.S. Cl.
CPC ...
H10N 70/068 (2023.02); H10B 61/00 (2023.02); H10B 63/80 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02); H10N 70/023 (2023.02); H10N 70/063 (2023.02); H10N 70/066 (2023.02); H10N 70/841 (2023.02);
Abstract
A memory device is provided. The memory device includes a memory stack on a first dielectric layer, and a sidewall spacer on the memory stack. The memory device further includes a conductive cap on the sidewall spacer and the memory stack and an upper metal line on the conductive cap and the sidewall spacer, wherein the upper metal line wraps around the conductive cap, sidewall spacer, and memory stack.