The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2023
Filed:
Oct. 12, 2020
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventor:
Ryuichi Oikawa, Tokyo, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/64 (2006.01); H05K 1/02 (2006.01); H01L 23/528 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 23/528 (2013.01); H01L 23/642 (2013.01); H01L 28/60 (2013.01); H05K 1/025 (2013.01); H05K 1/0231 (2013.01);
Abstract
A semiconductor device comprises a wiring substrate and a semiconductor chip. In the wiring substrate, a plurality of micro-elements each comprised of a stacked structure including a power supply pattern and a ground pattern is arranged at a predetermined interval. In each of the plurality of micro-elements, the power supply pattern is formed in a wiring layer located one layer above or one layer below a wiring layer in which the ground pattern is formed. A power supply potential is to be supplied to the power supply patter, and a ground potential is to be supplied to the ground patter.