The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2023

Filed:

Dec. 28, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Suguru Nishikawa, Osaka, JP;

Takehiko Amaki, Yokohama, JP;

Yoshihisa Kojima, Kawasaki, JP;

Shunichi Igahara, Fujisawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01);
Abstract

According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.


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