The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11748060 B1

Date of Patent:

Sep. 05, 2023

Filed:

Nov. 25, 2019

Method and apparatus for use in the design and manufacture of integrated circuits

Applicant:

Imagination Technologies Limited, Kings Langley, GB;

Inventors:

Theo Alan Drane, London, GB;

Wai-Chuen Cheung, London, GB;

Assignee:

Imagination Technologies Limited, Kings Langley, GB;

Attorneys:

Potomac Law Group, PLLC

Vincent M DeLuca

Primary Examiner:

Matthew D Sandifer

Int. Cl.

CPC ...

G06F 7/535 (2006.01); G06F 30/327 (2020.01); G06F 7/38 (2006.01); G06F 30/00 (2020.01); G06F 30/30 (2020.01);

U.S. Cl.

CPC ...

G06F 7/38 (2013.01); G06F 7/535 (2013.01); G06F 30/00 (2020.01); G06F 30/30 (2020.01); G06F 30/327 (2020.01);

Abstract

A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived.

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