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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11743603 B1

PDFFull Text
Date of Patent:
Aug. 29, 2023

Filed:

Nov. 29, 2017

Solid-state imaging device and information processing method of solid-state imaging device

Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventors:

Yusuke Minagawa, Tokyo, JP;

Taishin Yoshida, Tokyo, JP;

Marie Toyoshima, Kanagawa, JP;

Toru Akishita, Tokyo, JP;

Tomohiro Morimoto, Kanagawa, JP;

Masafumi Kusakawa, Tokyo, JP;

Ikuhiro Tamura, Kanagawa, JP;

Takahiro Akahane, Tokyo, JP;

Eiji Hirata, Tokyo, JP;

Yoshinobu Furusawa, Fukuoka, JP;

Assignee:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Attorney:

Wolf, Greenfield & Sacks, P.C.

Primary Examiner:

Albert H Cutler

Int. Cl.
CPC ...
H04N 25/00 (2023.01); G06F 21/72 (2013.01); G09C 1/00 (2006.01); H01L 27/146 (2006.01); H04N 25/633 (2023.01); H04L 9/32 (2006.01); H04N 25/65 (2023.01); H04N 25/67 (2023.01); H04N 25/79 (2023.01); H04N 25/75 (2023.01);
U.S. Cl.
CPC ...
H04N 25/00 (2023.01); G06F 21/72 (2013.01); G09C 1/00 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H04N 25/633 (2023.01); H04L 9/3231 (2013.01); H04N 25/65 (2023.01); H04N 25/67 (2023.01);
Abstract

A solid-state imaging device adapted to encrypt data is described. The solid-state imaging device may include a sensor die comprising an array of imaging pixels formed on a first side of the sensor die and first wiring layers formed on a second side of the sensor die, wherein at least one of the imaging pixels is configured to generate specific signals; a logic die comprising second wiring layers formed on a first side of the logic die; and an encryption processor on the logic die configured to generate encrypted data using the specific signals. The first side of the logic die may be mounted adjacent to the second side of the sensor die and the first wiring layers electrically connect to the second wiring layers, wherein the at least one of the imaging pixels, the encryption processor, and a connecting conductor in which the specific signals pass through from the at least one of the imaging pixels to the encryption processor are located interior to the solid-state imaging device.

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