The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2023

Filed:

Nov. 19, 2021
Applicant:

Psemi Corporation, San Diego, CA (US);

Inventors:

Poojan Wagh, Sleepy Hollow, IL (US);

Kashish Pal, Reading, GB;

Robert Mark Englekirk, Littleton, CO (US);

Tero Tapio Ranta, San Diego, CA (US);

Keith Bargroff, San Diego, CA (US);

Simon Edward Willard, Irvine, CA (US);

Assignee:

pSemi Corporation, San Diego, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/22 (2006.01); H03F 1/02 (2006.01); H03F 3/193 (2006.01);
U.S. Cl.
CPC ...
H03F 1/0211 (2013.01); H03F 1/0261 (2013.01); H03F 1/223 (2013.01); H03F 3/193 (2013.01); H03F 2200/18 (2013.01); H03F 2200/21 (2013.01); H03F 2200/451 (2013.01); H03F 2200/522 (2013.01);
Abstract

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.


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