The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2023

Filed:

Nov. 02, 2021
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventor:

Jar-Ming Ho, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/285 (2006.01); H01L 23/532 (2006.01); H01L 21/3213 (2006.01); H01L 23/544 (2006.01); H01L 21/768 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H01L 21/28506 (2013.01); H01L 21/3213 (2013.01); H01L 21/7682 (2013.01); H01L 23/5329 (2013.01); H01L 23/544 (2013.01); H10B 12/00 (2023.02); H10B 12/09 (2023.02); H10B 12/50 (2023.02);
Abstract

The present disclosure provides a method for preparing a semiconductor device. The method includes forming a first metal plug, a second metal plug, a third metal plug, and a fourth metal plug over a semiconductor substrate. The method also includes depositing a dielectric layer over the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug. A first portion of the dielectric layer extends between the first metal plug and the second metal plug such that the first portion of the dielectric layer and the semiconductor substrate are separated by an airgap while a second portion of the dielectric layer extends between the third metal plug and the fourth metal plug such that the second portion of the dielectric layer is in direct contact with the semiconductor substrate.


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