The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2023
Filed:
Mar. 25, 2020
Texas Instruments Incorporated, Dallas, TX (US);
Damien Thomas Gilmore, Allen, TX (US);
Jonathan P. Davis, Allen, TX (US);
Azghar H Khazi-Syed, Arlington, TX (US);
Shariq Arshad, Allen, TX (US);
Khanh Quang Le, Garland, TX (US);
Kaneez Eshaher Banu, Plano, TX (US);
Jonathan Roy Garrett, Garland, TX (US);
Sarah Elizabeth Bradshaw, Dallas, TX (US);
Eugene Clayton Davis, McKinney, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer.