The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2023

Filed:

Mar. 16, 2021
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Kazuhiko Segi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 29/51 (2006.01); H01L 21/266 (2006.01); H01L 21/265 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 21/022 (2013.01); H01L 21/0217 (2013.01); H01L 21/0228 (2013.01); H01L 21/02164 (2013.01); H01L 21/266 (2013.01); H01L 21/26506 (2013.01); H01L 21/28194 (2013.01); H01L 29/517 (2013.01);
Abstract

First, an offset spacer including a stacked film of insulating films is formed on the upper surface of the semiconductor layer, the side surface of the gate electrode, and the side surface of the cap film. Next, a part of the insulating films is removed to expose the upper surface of the semiconductor layer. Next, in a state where the side surface of the gate electrode is covered with the insulating films, an epitaxial layer is formed on the exposed upper surface of the semiconductor layer. Here, among the offset spacers, the insulating film which is a silicon nitride film is formed at a position closest to the gate electrode, and the position of the upper end of the insulating film formed on the side surface of the gate electrode is higher than the position of the upper surface of the gate electrode.


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