The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2023

Filed:

Jan. 18, 2023
Applicant:

Industrial Technology Research Institute, Hsinchu, TW;

Inventors:

Chih-Sheng Lin, Tainan, TW;

Jian-Wei Su, Hsinchu, TW;

Tuo-Hung Hou, Hsinchu, TW;

Sih-Han Li, New Taipei, TW;

Fu-Cheng Tsai, Tainan, TW;

Yu-Hui Lin, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/412 (2006.01); G06F 17/16 (2006.01);
U.S. Cl.
CPC ...
G06F 17/16 (2013.01); G11C 11/412 (2013.01);
Abstract

A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.


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