The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2023

Filed:

Mar. 09, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Isao Ooigawa, Kawasaki Kanagawa, JP;

Nariyuki Fukuda, Yokohama Kanagawa, JP;

Kazuhito Hosaka, Kawasaki Kanagawa, JP;

Tsutomu Miyamae, Yokohama Kanagawa, JP;

Takeshi Yamaguchi, Kamakura Kanagawa, JP;

Suguru Tahara, Yokohama Kanagawa, JP;

Keitarou Mishima, Yokohama Kanagawa, JP;

Yuichiro Sanuki, Urayasu Chiba, JP;

Koichi Kimura, Yokohama Kanagawa, JP;

Assignee:

Kioxia Corporation, Toyko, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318536 (2013.01); G01R 31/318541 (2013.01); G01R 31/318552 (2013.01); G01R 31/318555 (2013.01);
Abstract

A semiconductor device of the embodiment includes a plurality of scan chains, a shift clock control circuit, and a shift clock generation circuit. The plurality of scan chains each include a plurality of scan flip-flops. The shift clock control circuit outputs, to each of the plurality of scan chains, a control signal that non-inverts or inverts a scan clock signal. The shift clock generation circuit is provided to each of the plurality of scan flip-flops and generates a non-inverted scan clock signal or an inverted scan clock signal based on the control signal, the non-inverted scan clock signal being obtained by non-inverting the scan clock signal, the inverted scan clock signal being obtained by inverting the scan clock signal.


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