The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2023
Filed:
Oct. 04, 2021
Applicants:
Mikro Systems, Inc., Charlottesville, VA (US);
Siemens Energy, Inc., Orlando, FL (US);
Inventors:
Assignees:
SIEMENS ENERGY, INC., Orlando, FL (US);
MIKRO SYSTEMS, INC., Charlottesville, VA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
F01D 25/00 (2006.01); B22F 3/22 (2006.01); B22F 5/04 (2006.01); B22F 7/06 (2006.01); C23C 24/08 (2006.01); B22F 7/02 (2006.01); C04B 35/622 (2006.01); B22F 5/00 (2006.01);
U.S. Cl.
CPC ...
F01D 25/007 (2013.01); B22F 3/22 (2013.01); B22F 5/04 (2013.01); B22F 7/02 (2013.01); B22F 7/06 (2013.01); C04B 35/62222 (2013.01); C23C 24/08 (2013.01); F01D 25/005 (2013.01); B22F 2005/005 (2013.01); Y10T 428/12472 (2015.01); Y10T 428/239 (2015.01); Y10T 428/24355 (2015.01); Y10T 428/24529 (2015.01); Y10T 428/24545 (2015.01);
Abstract
A method of manufacturing a substrate () with a ceramic thermal barrier coating (). The interface between layers of the coating contains an engineered surface roughness () to enhance the mechanical integrity of the bond there between. The surface roughness is formed in a surface of a mold () and is infused by a subsequently cast layer of material (). The substrate may be partially sintered () prior to application of the coating layer(s) and the coated substrate and coating layer(s) may be co-sintered to form a fully coherent strain-free interlayer.