The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2023

Filed:

Feb. 11, 2022
Applicant:

Cisco Technology, Inc., San Jose, CA (US);

Inventors:

Ramana Rao Kompella, Cupertino, CA (US);

Chandra Nagarajan, Fremont, CA (US);

John Thomas Monk, Palo Alto, CA (US);

Purna Mani Kumar Ghantasala, Sunnyvale, CA (US);

Assignee:

Cisco Technology Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 41/0853 (2022.01); H04L 41/0893 (2022.01); H04L 41/14 (2022.01); H04L 41/0813 (2022.01); H04L 41/12 (2022.01); H04L 49/1515 (2022.01); H04L 45/64 (2022.01); H04L 47/2441 (2022.01); H04L 49/10 (2022.01); H04L 45/745 (2022.01);
U.S. Cl.
CPC ...
H04L 41/0853 (2013.01); H04L 41/0893 (2013.01); H04L 41/145 (2013.01); H04L 41/0813 (2013.01); H04L 41/12 (2013.01); H04L 45/64 (2013.01); H04L 45/74591 (2022.05); H04L 47/2441 (2013.01); H04L 49/10 (2013.01); H04L 49/1515 (2013.01);
Abstract

Systems, methods, and computer-readable media analyzing memory usage in a network node. A network assurance appliance may be configured to determine a hit count for a concrete level rule implemented on a node and identify one or more components of a logical model, wherein each of the one or more components are associated with the concrete level rule. The network assurance appliance may attribute the hit count for the concrete level rule to each of the components of the logical model, determine a number of hardware level entries associated with the each of the one or more components, and generate a report comprising the one or more components of the logical model, the hit count attributed to each of the one or more components of the logical model, and the number of hardware level entries associated with the one or more components of the logical model.


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