The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2023

Filed:

Oct. 27, 2022
Applicant:

Faraday Technology Corp., Hsin-Chu, TW;

Inventors:

Ko-Ching Chao, Hsin-Chu, TW;

Chih-Hung Wu, Hsin-Chu, TW;

Po-Wen Hsiao, Hsin-Chu, TW;

Zhou-Lun Liou, Hsin-Chu, TW;

Assignee:

Faraday Technology Corp., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01); G11C 11/4076 (2006.01); H03K 21/02 (2006.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
H03L 7/00 (2013.01); G11C 11/4076 (2013.01); H03K 19/21 (2013.01); H03K 21/023 (2013.01);
Abstract

A method for performing divided-clock phase synchronization in a multi-divided-clock system, an associated synchronization control circuit, an associated synchronization control sub-circuit and an associated electronic device are provided. The method may include: performing frequency division operations according to a source clock to generate a first divided clock and a second divided clock; performing phase relationship detection on the first divided clock according to the second divided clock to generate a phase relationship detection result signal; performing a logic operation on a first phase selection result output signal and the phase relationship detection result signal to generate a second phase selection result output signal; and outputting one of the second divided clock and an inverted signal of the second divided clock according to the second phase selection result output signal, for further use in a physical layer circuit.


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