The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 22, 2023
Filed:
Apr. 06, 2021
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Byounghak Hong, Albany, NY (US);
Seunghyun Song, Albany, NY (US);
Hwichan Jun, Albany, NY (US);
Inchan Hwang, Schenectady, NY (US);
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01); H01L 21/822 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0688 (2013.01); H01L 21/8221 (2013.01); H01L 21/823437 (2013.01); H01L 21/823487 (2013.01); H01L 21/823828 (2013.01); H01L 21/823885 (2013.01); H01L 27/0922 (2013.01); H01L 29/66545 (2013.01);
Abstract
A stacked semiconductor device includes: a substrate; a 1transistor formed on a substrate, and including a 1active region surrounded by a 1gate structure and 1source/drain regions; and a 2transistor stacked on the 1transistor, and including a 2active region surrounded by a 2gate structure and 2source/drain regions, wherein the 1active region and the 1gate structure are vertically mirror-symmetric to the 2active region and the 2gate structure, respectively, with respect to a virtual plane therebetween.