The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2023

Filed:

Sep. 09, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Tomohiko Ito, Kawasaki Kanagawa, JP;

Kazuto Uehara, Sagamihara Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/30 (2006.01); G11C 16/08 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/30 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/3459 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes a first memory cell and a first boosting circuit. The first boosting circuit generates a first voltage, a second voltage, and a third voltage lower than the second voltage at a first output terminal. The first, second and third voltages is used for a write operation. The write operation includes a first program operation and a first verify operation executed after the first program operation. The first boosting circuit generates the first voltage at the first output terminal during the first program operation, generates the third voltage at the first output terminal at end of the first program operation, generates the second voltage at the first output terminal during the first verify operation, and then generates the first voltage to the first output terminal during the first verify operation.


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