The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2023

Filed:

May. 14, 2018
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Chul Kyu Kang, Yongin-si, KR;

Yong Sung Park, Yongin-si, KR;

Jin Woo Park, Yongin-si, KR;

Dong Sun Lee, Yongin-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3266 (2016.01); G09G 3/3291 (2016.01); G11C 19/28 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3266 (2013.01); G09G 3/3291 (2013.01); G11C 19/28 (2013.01); G09G 2310/0202 (2013.01); G09G 2310/0286 (2013.01);
Abstract

A circuit stage including a first transistor including a first electrode and a gate electrode, the first electrode being coupled to a first input terminal and the gate electrode being coupled to a second input terminal configured to receive a first clock signal, an output circuit coupled to the second input terminal and a second power input terminal, an input circuit coupled to a second electrode of the first transistor and to a third input terminal, the third input terminal being configured to receive a first control clock signal, the input circuit being configured to control voltages of the second node and a third node, a first driving circuit coupled to a first power input terminal and to a fourth input terminal configured to receive a second control clock signal, and a second driving circuit coupled to the fourth input terminal and the third node.


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