The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2023

Filed:

Mar. 20, 2020
Applicant:

Axis Semiconductor, Inc., Methuen, MA (US);

Inventors:

Xiaolin Wang, Methuen, MA (US);

Qian Wu, Redwood City, CA (US);

Assignee:

Axis Semiconductor, Inc., Methuen, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4022 (2013.01);
Abstract

A computing device includes a transport switch comprising read and write switches that provide switched circuit interconnections between input and output ports for simultaneous data communication between a plurality of memory clients and a plurality of memory banks, such as between cores of a multi-core processor simultaneously accessing L1, L2, and L3 memory banks. Embodiments implement switching designs that are derived from existing switched network architectures. Other embodiments implement a novel circuit switch design based on 8×8 building blocks. The transport switch can be non-blocking, and can be self-routing. An additional switching layer can be included to provide port rearrangement for rearrangeable non-blocking switches. A transport compiler can be used to determine port-pair configurations of the switch. A disclosed method selects optimal switch architectures for specific applications. Embodiments support simultaneous, multicast transfers of data retrieved from a memory bank to a plurality of memory clients.


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