The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2023

Filed:

Feb. 13, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jae Min Kim, Suwon-si, KR;

Byungchul Jeon, Seongnam-si, KR;

Junho Huh, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 1/3287 (2019.01); G06F 11/30 (2006.01); G06F 11/34 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4893 (2013.01); G06F 1/3287 (2013.01); G06F 9/505 (2013.01); G06F 11/3024 (2013.01); G06F 11/3423 (2013.01); G06F 2209/486 (2013.01);
Abstract

In a method of operating a multi-core system comprising a plurality of processor cores, a plurality of task stall information respectively corresponding to a plurality of tasks are provided by monitoring a task stall time with respect to each task. The task stall time indicates a time while the each task is suspended within a task active time, and the task active time indicates a time while a corresponding processor core is occupied by the each task. Task scheduling is performed based on the plurality of task stall information, and a fine-grained dynamic voltage and frequency scaling (DVFS) is performed based on the task scheduling. The plurality of tasks may be assigned to the plurality of processor cores based on load unbalancing, and the effects of the fine-grained DVFS may be increased to reduce the power consumption of the multi-core system.


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