The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2023

Filed:

May. 21, 2021
Applicants:

Kratos Sre, Inc., San Diego, CA (US);

The University of Alabama IN Huntsville, Huntsville, AL (US);

Inventors:

Seth D. Cohen, Birmingham, AL (US);

Aubrey Beal, Huntsville, AL (US);

Assignees:

Kratos SRE, Inc., San Diego, CA (US);

The University of Alabama in Huntsville, Huntsville, AL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01S 13/10 (2006.01); H03K 3/037 (2006.01); G01S 7/282 (2006.01); H03K 5/01 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
G01S 13/106 (2013.01); G01S 7/282 (2013.01); H03K 3/037 (2013.01); H03K 5/01 (2013.01); H03K 2005/00078 (2013.01);
Abstract

Backend components for noise radar and techniques for operation of those components are provided. Some embodiments include noise radar apparatuses. A noise radar apparatus may include a first unit that generates a random signal or a broadband noise signal using asynchronous logic gates constituting the first unit. The noise radar apparatus also may include a second unit that generates a reference sequence using the generated random signal or the generated broadband noise signal. The second unit comprises at least one tapped delay line formed by second asynchronous logic gates having sampling functionality and storage functionality. The noise radar apparatus may further include a third unit that receives a return signal correlates the return signal and the reference sequence in nearly real-time using third asynchronous logic gates constituting the third unit.


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