The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2023

Filed:

Oct. 03, 2017
Applicant:

Sumco Corporation, Tokyo, JP;

Inventors:

Mami Kubota, Tokyo, JP;

Fumiya Fukuhara, Tokyo, JP;

Tomonori Miura, Tokyo, JP;

Assignee:

SUMCO CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B24B 37/08 (2012.01); B24B 37/28 (2012.01); H01L 21/02 (2006.01); B24B 37/20 (2012.01); B24B 37/04 (2012.01);
U.S. Cl.
CPC ...
B24B 37/20 (2013.01); B24B 37/042 (2013.01); B24B 37/28 (2013.01); H01L 21/02016 (2013.01); H01L 21/02024 (2013.01);
Abstract

Provided is a method of double-side polishing a semiconductor wafer, which can suppress variation in the polishing quality by providing for changes in the polishing environment during polishing. The method of double-side polishing of a semiconductor wafer includes: a step of predetermining a criterion function for determining polishing tendencies of double-side polishing; a first step of starting double-side polishing of the semiconductor wafer under initial polishing conditions; a second step of while performing double-side polishing on the semiconductor wafer under the initial polishing conditions, calculating a value of the criterion function using the apparatus log data in a predetermined period of polishing in the first step, and setting on the double-side polishing apparatus polishing conditions obtained by adjusting the initial polishing conditions based on the value of the criterion function; and a third step of performing double-side polishing of the semiconductor wafer under the adjusted polishing conditions.


Find Patent Forward Citations

Loading…