The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2023

Filed:

Oct. 12, 2021
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Jae-Hyun Han, Icheon-si, KR;

Hyang-Keun Yoo, Seongnam-si, KR;

Se-Ho Lee, Yongin-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 63/00 (2023.01); G11C 5/06 (2006.01); G11C 13/00 (2006.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
H10B 63/84 (2023.02); G11C 5/06 (2013.01); G11C 13/0002 (2013.01); H10N 70/826 (2023.02);
Abstract

An electronic device including a semiconductor memory is provided. The semiconductor memory includes: a substrate having a substantially horizontal upper surface; first to Nth layers (where N is a natural number of two or more) disposed in horizontal layers on the substrate and spaced apart from each other above the substrate in a vertical direction, wherein each of the first to Nth layers includes a plurality of conductive lines; an insulating layer disposed to fill spaces between the conductive lines; a hole having sidewalls that extends in the vertical direction through the conductive lines of the first to Nth layers and the insulating layer therebetween; a variable resistance layer disposed on the sidewalls of the hole; and a conductive pillar disposed to fill the hole in which the variable resistance layer is formed.


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