The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2023
Filed:
Dec. 29, 2020
Applicant:
Iu-meng Tom Ho, Milpitas, CA (US);
Inventor:
Iu-Meng Tom Ho, Milpitas, CA (US);
Assignee:
Other;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/30 (2023.01); G11C 11/22 (2006.01); H01L 29/78 (2006.01); H10B 51/10 (2023.01);
U.S. Cl.
CPC ...
H10B 51/30 (2023.02); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); H01L 29/78391 (2014.09); H10B 51/10 (2023.02);
Abstract
A depletion-mode FeFET ('FeDFET') is programmable to a first programmed state, under a first set of voltage biasing conditions, and to a second programmed state, under a second set of voltage biasing conditions. In both the first and second programmed states, the storage transistor has a threshold voltage that is not greater than 0 volts. A memory circuit may be organized as memory cells, with each memory cell including select transistors, transistor switches and FeDFETs in a static random-access memory (SRAM) cell configuration.