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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11729985 B1

PDFFull Text
Date of Patent:
Aug. 15, 2023

Filed:

Sep. 11, 2020

Semiconductor memory device

Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Kojiro Shimizu, Yokkaichi, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Mary A Wilczewski

Assistant Examiner:

Tsz K Chiu

Int. Cl.
CPC ...
H01L 27/112 (2006.01); H01L 27/11578 (2017.01); H01L 21/768 (2006.01); H10B 43/50 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H10B 43/50 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02);
Abstract

According to one embodiment, a semiconductor memory device includes first to second areas, a plurality of conductive layers, first to fourth members, and a plurality of pillars. The second area includes a first contact area including first to third sub-areas. The conductive layers include first to fourth conductive layers. The first conductive layer includes a first terrace portion in the first sub-area. The second conductive layer includes a second terrace portion in the third sub-area. The third conductive layer includes a third terrace portion in the first sub-area. The fourth conductive layer includes a fourth terrace portion in the third sub-area.

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