The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2023

Filed:

Jun. 03, 2022
Applicant:

Te Connectivity Solutions Gmbh, Schaffhausen, CH;

Inventors:

Justin Dennis Pickel, Hummelstown, PA (US);

Margaret Mahoney Fernandes, West Chester, PA (US);

Timothy Robert Minnick, Enola, PA (US);

Assignee:

TE CONNECTIVITY SOLUTIONS GMBH, Schaffhausen, CH;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 1/02 (2006.01); H01R 12/58 (2011.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0222 (2013.01); H05K 1/116 (2013.01); H01R 12/58 (2013.01); H05K 1/18 (2013.01); H05K 2201/09481 (2013.01); H05K 2201/09609 (2013.01); H05K 2201/09772 (2013.01); H05K 2201/10189 (2013.01); H05K 2201/10901 (2013.01);
Abstract

A printed circuit board includes a layered substrate having a plurality of layers having an electrical connector footprint configured to receive an electrical connector. The printed circuit board includes pair anti-pads passing through the layered substrate around pairs of signal vias. The printed circuit board includes ground vias passing through the layered substrate. The ground vias are configured to receive ground pins of the electrical connector. The ground vias are located outside of the pair anti-pads. The printed circuit board includes SI vias passing through the layered substrate. The SI vias form an SI fence surrounding the corresponding pair anti-pad.


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