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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11728447 B1

PDFFull Text
Date of Patent:
Aug. 15, 2023

Filed:

May. 21, 2021

Semiconductor device and imaging apparatus

Applicant:

Sony Group Corporation, Tokyo, JP;

Inventor:

Makoto Murai, Tokyo, JP;

Assignee:

SONY GROUP CORPORATION, Tokyo, JP;

Attorney:

Chip Law Group

Primary Examiner:

Mohammed Shamsuzzaman

Int. Cl.
CPC ...
H01L 31/024 (2014.01); H01L 27/14 (2006.01); H01L 25/10 (2006.01); H01L 25/11 (2006.01); H01L 25/18 (2023.01); H01L 25/00 (2006.01); H01L 31/0224 (2006.01); H01L 31/0203 (2014.01); H01L 27/146 (2006.01); H04N 23/54 (2023.01); H04N 23/55 (2023.01);
U.S. Cl.
CPC ...
H01L 31/024 (2013.01); H01L 25/10 (2013.01); H01L 25/105 (2013.01); H01L 25/11 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 27/14 (2013.01); H01L 27/1469 (2013.01); H01L 27/14618 (2013.01); H01L 27/14625 (2013.01); H01L 27/14627 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 31/0203 (2013.01); H01L 31/0224 (2013.01); H04N 23/54 (2023.01); H04N 23/55 (2023.01); H01L 2224/16225 (2013.01); H01L 2225/1017 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1094 (2013.01);
Abstract

In a semiconductor device, a first package is provided with a first substrate under which a semiconductor chip configured to output a signal and a first wiring electrically connected to the semiconductor chip are arranged. A second package is provided with a second substrate above which a processing circuit configured to process the output signal, a second wiring electrically connected to the processing circuit, and an encapsulant configured to seal the processing circuit are arranged, the semiconductor chip and the encapsulant being arranged to face each other in a non-contact manner. A connection portion electrically connects the first wiring and the second wiring.

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