Ternary memory cell for logic-in-memory and memory device comprising same

Abstract

According to an embodiment of the present disclosure, a memory device for a logic-in-memory may include a cell array including a plurality of ternary memory cells, a row decoder configured to select at least one ternary memory cell from among the plurality of ternary memory cells, and a page buffer configured to provide a first value to the at least one ternary memory cell and latch a third value obtained by performing a logic operation on the first value and a second value stored in the at least one ternary memory cell and/or the second value. The at least one ternary memory cell may include: a first inverter and a second inverter, cross-coupled in a first node corresponding to the second value and a second node corresponding to an inverted value of the second value, and including a pull-up device and a pull-down device, wherein the pull-up device and the pull-down device are configured to have a constant current pass therethrough upon turn-off; and a logic operation circuit including a P-channel transistor and an N-channel transistor and configured to output the third value, wherein the P-channel transistor and the N-channel transistor are configured to have the constant current pass therethrough upon turn-off.