The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2023

Filed:

May. 12, 2020
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Michael W. Murphy, Menlo Park, CA (US);

Gopal Thirumalai Narayanan, Santa Clara, CA (US);

Deepak K. Mishra, Irvine, CA (US);

Andre M. Glover, San Jose, CA (US);

Sreenivas Tallam, San Jose, CA (US);

Hardik K. Doshi, Los Altos, CA (US);

Assignee:

APPLE INC., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 13/42 (2006.01); G06F 13/40 (2006.01); H04L 47/125 (2022.01);
U.S. Cl.
CPC ...
G06F 9/5083 (2013.01); G06F 9/505 (2013.01); G06F 13/4022 (2013.01); G06F 13/4027 (2013.01); G06F 13/4221 (2013.01); G06F 13/4282 (2013.01); H04L 47/125 (2013.01); G06F 2213/0024 (2013.01); G06F 2213/0026 (2013.01);
Abstract

A method and apparatus of a device that load balances a first plurality of Peripheral Connect Interconnect ports is described. In an exemplary embodiment, the device detects a second plurality of PCI ports in the device. In addition, the device determines a load for each port in the first and second plurality of PCI ports and sorts the second plurality of PCI ports. The device further load balances the first plurality of PCI ports using at least a PCIe switch and the load determination of the second plurality of PCI ports. The device additionally communicates data between the first and second plurality of PCI ports.


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