The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2023

Filed:

Sep. 23, 2020
Applicant:

Realtek Semiconductor Corp., Hsinchu, TW;

Inventors:

Yu-Pin Lin, Hsinchu, TW;

Lien-Hsiang Sung, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/3187 (2006.01); G11C 29/44 (2006.01); G11C 29/14 (2006.01); G11C 13/00 (2006.01); G11C 11/406 (2006.01); G06F 11/14 (2006.01); G06F 11/00 (2006.01); G11C 16/34 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3187 (2013.01); G11C 29/14 (2013.01); G11C 29/4401 (2013.01); G06F 11/002 (2013.01); G06F 11/1441 (2013.01); G11C 5/148 (2013.01); G11C 11/40618 (2013.01); G11C 11/40622 (2013.01); G11C 13/0033 (2013.01); G11C 16/3418 (2013.01);
Abstract

An integrated circuit self-repair method and an integrated circuit thereof are provided. The integrated circuit self-repair method includes: transmitting, by a main register, a predetermined logic state to at least three registers, and setting the at least three registers to the predetermined logic state; outputting, according to the predetermined logic state in the at least three registers, the predetermined logic state to drive a controlled circuit to perform a function; and when a minority of the at least three registers are changed to an opposite logic state due to an emergency occurring at an input power source, outputting the predetermined logic state according to the predetermined logic state of the remaining registers, and transmitting the predetermined logic state back to the register that is in the opposite logic state, to correct the opposite logic state to the predetermined logic state.


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