The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2023

Filed:

Sep. 28, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Ga Eun Kim, Yongin-si, KR;

Yoon Hwan Son, Seoul, KR;

Sung Won Cho, Seoul, KR;

Joo Hee Park, Suwon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01); H10B 43/10 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H10B 43/10 (2023.02); H10B 43/40 (2023.02); H10B 43/50 (2023.02);
Abstract

A semiconductor memory device and a method for fabricating a semiconductor memory device, the device including a peripheral logic structure on a substrate; a horizontal conductive substrate on the peripheral logic structure; a stacked structure including a plurality of electrode pads stacked in a vertical direction; a plate contact plug connected to the horizontal conductive substrate; and a first penetration electrode connected to the lower connection wiring body, wherein upper surfaces of the plate contact plug and the first penetration electrode are on a same plane, the plate contact plug includes an upper part and a lower part directly connected to each other, the first penetration electrode includes an upper part and a lower part directly connected to each other, moving away from upper surfaces of the first penetration electrode and the plate contact plug, widths of the upper parts increase and widths of the lower parts decrease.


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