The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2023

Filed:

Nov. 16, 2022
Applicant:

Rivian Ip Holdings, Llc, Plymouth, MI (US);

Inventors:

Steven E. Schulz, Torrance, CA (US);

David Tang, Rancho Cucamonga, CA (US);

Daniel L. Kowalewski, Redondo Beach, CA (US);

Silva Hiti, Redondo Beach, CA (US);

Assignee:

Rivian IP Holdings, LLC, Plymouth, MI (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02P 27/08 (2006.01); H02M 7/5395 (2006.01); H02M 1/00 (2006.01); H02K 7/00 (2006.01);
U.S. Cl.
CPC ...
H02P 27/085 (2013.01); H02M 1/0043 (2021.05); H02M 7/5395 (2013.01); H02K 7/006 (2013.01);
Abstract

A controller includes a first processor for a first power inverter. Computer-readable media is configured to store computer-executable instructions configured to cause the first processor to: generate a first clock signal and a second clock signal; identify a pulse width modulation method of the first power inverter and a pulse width modulation method of a second power inverter; identify and compare a switching frequency of the first power inverter and a switching frequency of the second power inverter; determine an optimized phase shift between the first power inverter and the second power inverter responsive to the pulse width modulation method of the first power inverter and the pulse width modulation method of the second power inverter and the switching frequency of the first power inverter and the switching frequency of the second power inverter; and synchronize the optimized phase shift between the first power inverter and the second power inverter. A second processor for the second power inverter is configured to receive the second clock signal.


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