The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2023

Filed:

Nov. 28, 2019
Applicants:

Hefei Boe Display Technology Co., Ltd., Anhui, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Yue Du, Beijing, CN;

Wei Guo, Beijing, CN;

Ke Dai, Beijing, CN;

Lei Guo, Beijing, CN;

Liangliang Jiang, Beijing, CN;

Jiaqing Liu, Beijing, CN;

Yuanhui Guo, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1337 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G02F 1/1343 (2006.01);
U.S. Cl.
CPC ...
G02F 1/133707 (2013.01); G02F 1/1368 (2013.01); G02F 1/134336 (2013.01); G02F 1/136286 (2013.01);
Abstract

The present disclosure provides an array substrate, a dimming liquid crystal panel and a display panel. The array substrate includes: a first transparent electrode layer with a plurality of slit structures, wherein the first transparent electrode layer comprises a plurality of domains, the plurality of domains comprise at least two types of domains, each of the plurality of domains is adjacent to different types of domains along both a row direction and a column direction; and a plurality of gate lines extending along the row direction and a plurality of data lines extending along the column direction, the plurality of gate lines and the plurality of data lines crossing to define a plurality of dimming regions arranged in an array.


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