The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2023

Filed:

Aug. 08, 2022
Applicant:

Seeqc, Inc., Elmsford, NY (US);

Inventors:

Oleg A. Mukhanov, Putnam Valley, NY (US);

Alexander F. Kirichenko, Pleasantville, NY (US);

Igor V. Vernik, Yorktown Heights, NY (US);

Ivan P. Nevirkovets, Evanston, IL (US);

Alan M. Kadin, Princeton Junction, NJ (US);

Assignee:

SeeQC, Inc., Elmsford, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
A61K 8/73 (2006.01); A61K 8/42 (2006.01); A61K 8/02 (2006.01); A61Q 19/00 (2006.01); A61K 8/34 (2006.01); A61K 8/20 (2006.01); A61Q 19/08 (2006.01); A61K 8/25 (2006.01); G06N 10/00 (2022.01); G01R 33/035 (2006.01); G01R 33/12 (2006.01); G11C 11/16 (2006.01); G11C 11/18 (2006.01); G11C 11/44 (2006.01); G11C 7/10 (2006.01); H01L 27/18 (2006.01); H01L 39/22 (2006.01);
U.S. Cl.
CPC ...
A61K 8/733 (2013.01); A61K 8/0212 (2013.01); A61K 8/20 (2013.01); A61K 8/25 (2013.01); A61K 8/345 (2013.01); A61K 8/42 (2013.01); A61Q 19/00 (2013.01); A61Q 19/08 (2013.01); G01R 33/0354 (2013.01); G01R 33/1284 (2013.01); G06N 10/00 (2019.01); G11C 11/161 (2013.01); G11C 11/1653 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/18 (2013.01); G11C 11/44 (2013.01); G11C 7/1006 (2013.01); G11C 7/1075 (2013.01); G11C 2207/007 (2013.01); H01L 27/18 (2013.01); H01L 39/223 (2013.01);
Abstract

A system and method for high-speed, low-power cryogenic computing are presented, comprising ultrafast energy-efficient RSFQ superconducting computing circuits, and hybrid magnetic/superconducting memory arrays and interface circuits, operating together in the same cryogenic environment. An arithmetic logic unit and register file with an ultrafast asynchronous wave-pipelined datapath is also provided. The superconducting circuits may comprise inductive elements fabricated using both a high-inductance layer and a low-inductance layer. The memory cells may comprise superconducting tunnel junctions that incorporate magnetic layers. Alternatively, the memory cells may comprise superconducting spin transfer magnetic devices (such as orthogonal spin transfer and spin-Hall effect devices). Together, these technologies may enable the production of an advanced superconducting computer that operates at clock speeds up to 100 GHz.


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