The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2023

Filed:

Nov. 22, 2021
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Chang Joon Park, Sunnyvale, CA (US);

Martin Francis Galinski, III, Mountain View, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/158 (2006.01); H02M 3/07 (2006.01); H02M 1/00 (2006.01); G09G 3/36 (2006.01); G01R 19/165 (2006.01); G02B 27/01 (2006.01); G05F 1/575 (2006.01);
U.S. Cl.
CPC ...
H02M 3/1584 (2013.01); G01R 19/16538 (2013.01); G02B 27/017 (2013.01); G05F 1/575 (2013.01); G09G 3/3696 (2013.01); H02M 1/0025 (2021.05); H02M 3/071 (2021.05);
Abstract

A power supply device includes a switching converter, an inductor, and a linear voltage regulator. The inductor is electrically connected between a first switching node and a second switching node of the switching converter. The power supply device is configured such that when the switching converter is in an ON state the inductor is charged with a charging current. The power supply device is further configured such that when the switching converter is in an OFF state, the switching converter modulates an input voltage to generate a positive-bias output voltage at a positive-bias output node, the charging current flows from the inductor such that a negative input voltage is generated at a linear voltage regulator input node, and the linear voltage regulator regulates the negative input voltage to generate a negative-bias output voltage at a negative-bias output node.


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