The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2023

Filed:

Aug. 11, 2021
Applicant:

Murata Manufacturing Co., Ltd., Kyoto-fu, JP;

Inventor:

Kenji Sasaki, Nagaokakyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/737 (2006.01); H01L 23/00 (2006.01); H01L 29/205 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7371 (2013.01); H01L 24/13 (2013.01); H01L 29/0826 (2013.01); H01L 29/205 (2013.01); H01L 2224/13025 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/10338 (2013.01); H01L 2924/13051 (2013.01);
Abstract

At least one transistor is arranged on a substrate. A collector layer and a base layer of the transistor compose a collector mesa having a substantially mesa shape and the collector mesa has side faces tilting with respect to the substrate so that the dimension of a top face in a first direction of a plane of the substrate is smaller than the dimension of a bottom face therein. A first insulating film covering the transistor is arranged on the substrate. A first-layer emitter line that extends from an area overlapped with the top face of the collector mesa to areas overlapped with at least part of the tilting side faces of the collector mesa in a plan view is arranged on the first insulating film. A second-layer emitter line and an emitter bump are arranged on the first-layer emitter line.


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