The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2023

Filed:

Jan. 25, 2021
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Yee Gin Tea, Bukit Katil, MY;

Chong Han Lim, Seri Kembangan, MY;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49548 (2013.01); H01L 21/4825 (2013.01); H01L 21/4828 (2013.01); H01L 21/565 (2013.01); H01L 23/3107 (2013.01); H01L 23/3114 (2013.01); H01L 23/4952 (2013.01); H01L 23/49503 (2013.01); H01L 23/49513 (2013.01); H01L 23/49541 (2013.01); H01L 23/49582 (2013.01); H01L 24/06 (2013.01); H01L 2924/181 (2013.01);
Abstract

In some examples, a semiconductor package comprises a die pad, a semiconductor die on the die pad, and a mold compound covering the die pad and the semiconductor die. The semiconductor package includes a conductive component including a roughened surface, the roughened surface having a roughness ranging from an arithmetic mean surface height (SA) of 1.4 to 3.2. The mold compound is coupled to the roughened surface. The semiconductor package includes a bond wire coupling the semiconductor die to the roughened surface. The bond wire is directly coupled to the roughened surface without a precious metal positioned therebetween.


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