The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2023

Filed:

Aug. 26, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Kazutaka Ikegami, Inagi Tokyo, JP;

Hidehiro Shiga, Yokohama Kanagawa, JP;

Takashi Maeda, Kamakura Kanagawa, JP;

Rieko Funatsuki, Yokohama Kanagawa, JP;

Takayuki Miyazaki, Setagaya Tokyo, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/08 (2006.01); G11C 16/30 (2006.01); G11C 16/20 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/20 (2013.01); G11C 16/30 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02);
Abstract

A semiconductor storage device includes a semiconductor pillar, a first string having first memory cells connected in series, first word lines connected to the first memory cells, a second string having second memory cells connected in series, and second word lines connected to the second memory cells. Each of the first memory cells faces, and shares a channel in the semiconductor pillar with, one of the second memory cells. When reading data of the k-th first memory cell, a voltage of the first word line connected to the k-th first memory cell reaches a first voltage at a first timing, and a voltage of the second word line connected to at least one of the second memory cells other than the k-th second memory cell in the second string facing the k-th first memory cell reaches the first voltage at a second timing that is later than the first timing.


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