The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2023

Filed:

Apr. 15, 2021
Applicant:

Dell Products, Lp, Round Rock, TX (US);

Inventors:

Wan-Ju Kuo, Xindian District, TW;

Douglas Winterberg, Austin, TX (US);

Bhyrav Mutnury, Austin, TX (US);

Assignee:

Dell Products L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 11/10 (2006.01); G06F 11/07 (2006.01); G06F 13/16 (2006.01); G06F 11/30 (2006.01); G06F 11/34 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06F 11/076 (2013.01); G06F 11/0772 (2013.01); G06F 11/3037 (2013.01); G06F 11/3466 (2013.01); G06F 13/1689 (2013.01);
Abstract

An information handling system includes a dual in-line memory module (DIMM) and a memory controller coupled to the DIMM via a data bus. The memory controller determines that a first lane of a byte group of the data bus is more susceptible to crosstalk than a second lane of the byte group, determines a first performance level of the first lane, changes a delay (D) of a third lane of the byte group, the third lane being adjacent to the first lane, and determines that a second performance level of the first lane is different from the first performance level in response to delaying the third lane.


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