The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2023
Filed:
Sep. 23, 2020
Superfastfpga Limited, London, GB;
Paul James Metzgen, London, GB;
SUPERFASTFPGA LIMITED, Putney, GB;
Abstract
A logic circuit comprising: inputs for receiving multiple n-bit numbers, n being greater than one; and an adder capable of receiving m n-bit numbers, m being greater than one, and forming an output representing the sum of those numbers, the adder having a plurality of single-bit stages and being configured to form the sum by subjecting successive bits of each of the numbers to an operation in a respective one of the single-bit stages, the single-bit stages being such that the adder has insufficient capacity to add all possible combinations of bits in a respective bit position of m n-bit numbers; the addition circuit being configured to add the multiple n-bit numbers by: in the adder, adding a first one of the n-bit numbers to a value corresponding to a set of non-consecutive bits of another of the n-bit numbers to form a first intermediate value; adding the first intermediate value to a value corresponding to the bits of the said other of the n-bit numbers other than those in the said set to form a sum; and outputting the sum.