The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2023

Filed:

Nov. 12, 2019
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken, JP;

Inventors:

Kei Takahashi, Kanagawa, JP;

Yuki Okamoto, Kanagawa, JP;

Minato Ito, Kanagawa, JP;

Takahiko Ishizu, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02J 7/00 (2006.01); G01R 31/396 (2019.01); H01M 10/48 (2006.01);
U.S. Cl.
CPC ...
G01R 31/396 (2019.01); H01M 10/48 (2013.01); H02J 7/0042 (2013.01); H02J 7/00712 (2020.01);
Abstract

A semiconductor device that tests and/or monitors each of batteries provided in an assembled battery is provided. The semiconductor device includes a hysteresis comparator and a circuit, and the circuit has a function of setting a high-level side threshold voltage and a low-level side voltage of the hysteresis comparator. The circuit includes first and second capacitors. A first terminal of the first capacitor is electrically connected to a high-level side reference potential input terminal of the hysteresis comparator and a first terminal of the second capacitor is electrically connected to a low-level side reference potential input terminal of the hysteresis comparator. After a first reference potential is input to the high-level side reference potential input terminal and a second reference potential is input to the low-level side reference potential input terminal, a negative electrode of a cell is electrically connected to each second terminal of the first and second capacitors, whereby the potential of each first terminal of the first and second capacitors is changed.


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