The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2023

Filed:

May. 13, 2021
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Shipei Li, Beijing, CN;

Sheng Xu, Beijing, CN;

Wei He, Beijing, CN;

Ying Zhao, Beijing, CN;

Huili Wu, Beijing, CN;

Fang He, Beijing, CN;

Renquan Gu, Beijing, CN;

Lizhen Zhang, Beijing, CN;

Yi Zhou, Beijing, CN;

Wusheng Li, Beijing, CN;

Qi Yao, Beijing, CN;

Yang Yue, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/32 (2006.01); H10K 59/123 (2023.01); H10K 59/122 (2023.01); H10K 59/124 (2023.01); H10K 71/00 (2023.01); H10K 59/12 (2023.01);
U.S. Cl.
CPC ...
H10K 59/123 (2023.02); H10K 59/122 (2023.02); H10K 59/124 (2023.02); H10K 71/00 (2023.02); H10K 59/1201 (2023.02);
Abstract

The present disclosure relates to the field of display technology, and proposes a display panel, a preparation method thereof, and a display apparatus. The display panel includes an array substrate, a planarization layer group, and a plurality of sub-pixels. The array substrate includes a switch array formed by a plurality of switch units. The planarization layer group is provided on the array substrate, and nano-scale grooves are provided on the planarization layer group. The sub-pixels are provided on a side of the planarization layer group away from the array substrate. The sub-pixel includes a plurality of first electrodes, wherein the first electrode is connected to the switch unit of the array substrate, a nano-scale second gap is provided between two adjacent first electrodes, and an orthographic projection of the second gap on the array substrate is located within an orthographic projection of the groove on the array substrate.


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