The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 25, 2023
Filed:
Oct. 27, 2021
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventor:
Roswald Francis, Kildare, IE;
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/01 (2006.01); H03K 19/0185 (2006.01); H03K 19/17788 (2020.01); H03K 19/17736 (2020.01); H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
H03K 19/01855 (2013.01); H03K 19/0016 (2013.01); H03K 19/1774 (2013.01); H03K 19/17788 (2013.01);
Abstract
Techniques and apparatus for reducing low frequency power supply spurs in clock signals in a clock distribution network. One example circuit for clock distribution generally includes a plurality of logic inverters coupled in series and configured to drive a clock signal and a current-starved inverter coupled in parallel (or in series) with a logic inverter in the plurality of logic inverters.
Quick Actions:
Francis, Roswald. (2023). Low frequency power supply spur reduction in clock signals (U.S. Patent No. 11711081). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11711081
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile