The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2023

Filed:

Oct. 20, 2021
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Michael John Shay, Fairview, TX (US);

Jonathan Lee Valdez, Bedford, TX (US);

Kyle Edward Addington, Richardson, TX (US);

Padmakumar Menon Nambiyath, Richardson, TX (US);

Huang Huanzhang, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/003 (2006.01); H03K 3/012 (2006.01); H04L 25/02 (2006.01);
U.S. Cl.
CPC ...
H03K 19/00361 (2013.01); H03K 3/012 (2013.01); H03K 19/00384 (2013.01); H04L 25/028 (2013.01);
Abstract

An integrated circuit includes first and second bus terminals, a pass-gate transistor, first and rising time accelerator (RTA) control circuits, and first and second falling time accelerator (FTA) control circuits. The pass-gate transistor couples between the first and second bus terminals. The first RTA control circuit couples to the first bus terminal, detects a rising edge on the first bus terminal, and accelerates the rising edge on the first bus terminal. The first FTA control circuit couples to the first bus terminal, detects a falling edge on the first bus terminal having a slope below a threshold, and accelerates the falling edge on the first bus terminal. The second RTA and FTA control circuits function similar to the first RTA and FTA control circuits but with respect to the second bus terminal.


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