The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2023

Filed:

Jun. 25, 2019
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

William Paul Hovis, Sammamish, WA (US);

Gregory M. Daly, Seattle, WA (US);

Rich Tat An, Renton, WA (US);

Andres Felipe Hernandez Mojica, Seattle, WA (US);

Garrett Douglas Blankenburg, Sammamish, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 1/32 (2019.01); H01L 25/18 (2023.01); G01R 31/28 (2006.01); G06F 1/3296 (2019.01); H01L 23/48 (2006.01); H01L 23/66 (2006.01); H01L 23/00 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); G06F 9/4401 (2018.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); G01R 31/2896 (2013.01); G06F 1/3296 (2013.01); H01L 23/481 (2013.01); H01L 23/66 (2013.01); H01L 24/16 (2013.01); H05K 1/113 (2013.01); H05K 1/181 (2013.01); G06F 9/4406 (2013.01); H01L 2223/6666 (2013.01); H01L 2224/16146 (2013.01); H05K 2201/10378 (2013.01); H05K 2201/10545 (2013.01);
Abstract

Power control and decoupling capacitance arrangements for integrated circuit devices are discussed herein. In one example, an assembly includes a first circuit assembly comprising a first circuit board coupled to an integrated circuit device, wherein the first circuit board is coupled to first surface of a system circuit board. The assembly also includes a second circuit assembly comprising a second circuit board having one or more voltage adjustment units configured to supply at least one input voltage to the integrated circuit device, wherein the second circuit board is coupled to a second surface of the system circuit board and positioned at least partially under a footprint of the integrated circuit device with respect to the system circuit board.


Find Patent Forward Citations

Loading…