The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2023

Filed:

Feb. 23, 2022
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventors:

Hsih-Yang Chiu, Taoyuan, TW;

Tse-Yao Huang, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/525 (2006.01); H01L 23/535 (2006.01); H01L 21/3215 (2006.01); H01L 29/92 (2006.01); H01L 21/28 (2006.01); H01L 29/40 (2006.01); H01L 23/532 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5252 (2013.01); H01L 21/28158 (2013.01); H01L 21/3215 (2013.01); H01L 23/535 (2013.01); H01L 29/401 (2013.01); H01L 29/92 (2013.01); H01L 23/53271 (2013.01); H01L 29/495 (2013.01);
Abstract

The present application discloses a semiconductor device with a programmable unit and a method for fabricating the semiconductor device. The semiconductor device including a substrate, a bottom conductive layer positioned in the substrate, a first gate structure including a first gate dielectric layer positioned on the bottom conductive layer, a first work function layer positioned on the first gate dielectric layer, and a first filler layer positioned on the first work function layer, a second gate structure including a second gate dielectric layer positioned on the bottom conductive layer and spaced apart from the first gate dielectric layer, a second work function layer positioned on the second gate dielectric layer, and a second filler layer positioned on the second work function layer, a conductive plug electrically coupled to the bottom conductive layer, and a top conductive layer electrically coupled to the first gate structure and the second gate structure.


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