The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2023

Filed:

Oct. 04, 2021
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Yong-Woo Lee, Gyeonggi-do, KR;

Min-Chang Kim, Gyeonggi-do, KR;

Chang-Hyun Kim, Gyeonggi-do, KR;

Do-Yun Lee, Gyeonggi-do, KR;

Jae-Jin Lee, Gyeonggi-do, KR;

Hun-Sam Jung, Gyeonggi-do, KR;

Chan-Jong Woo, Seoul, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0868 (2016.01); G06F 12/0893 (2016.01); G06F 13/00 (2006.01); G06F 12/0875 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0868 (2013.01); G06F 12/0875 (2013.01); G06F 12/0893 (2013.01); G06F 13/00 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/214 (2013.01); G06F 2212/451 (2013.01); Y02D 10/00 (2018.01);
Abstract

A memory system includes: a first memory module including first volatile memories; a second memory module including second volatile memories, non-volatile memories and a module controller; a memory controller controlling the first and second memory modules through second and third control buses, respectively; and a switch array electrically coupling the second and third control buses, wherein the module controller controls the switch array to electrically couple the second and third control buses in a backup operation for backing up data of the first volatile memories to the non-volatile memories, wherein the first and second memory modules include one or more first memory stacks and one or more second memory stacks, respectively, wherein the first volatile memories are stacked in the first memory stacks, and wherein the second volatile memories, the non-volatile memories and the module controller are stacked in the second memory stacks.


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