The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2023

Filed:

Nov. 13, 2020
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

John G. Dorsey, San Francisco, CA (US);

Andrei Dorofeev, San Jose, CA (US);

Keith Cox, Sunnyvale, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/30 (2006.01); G06F 11/07 (2006.01); G06F 11/34 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 11/3024 (2013.01); G06F 9/5094 (2013.01); G06F 11/076 (2013.01); G06F 11/3058 (2013.01); G06F 11/3409 (2013.01);
Abstract

A device implementing adaptive memory performance control by thread group may include a memory and at least one processor. The at least one processor may be configured to execute a group of threads on one or more cores. The at least one processor may be configured to monitor a plurality of metrics corresponding to the group of threads executing on one or more cores. The metrics may include, for example, a core stall ratio and/or a power metric. The at least one processor may be configured to determine, based at least in part on the plurality of metrics, a memory bandwidth constraint with respect to the group of threads executing on the one or more cores. The at least one processor may be configured to, in response to determining the memory bandwidth constraint, increase a memory performance corresponding to the group of threads executing on the one or more cores.


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