The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2023

Filed:

Mar. 09, 2022
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Prakash Narayanan, Karnataka, IN;

Sundarrajan Rangachari, Karnataka, IN;

Prashanth Saraf, Karnataka, IN;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/3183 (2006.01); G01R 31/3185 (2006.01); G01R 31/3181 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318307 (2013.01); G01R 31/31726 (2013.01); G01R 31/31727 (2013.01); G01R 31/31813 (2013.01); G01R 31/318552 (2013.01); G01R 31/318558 (2013.01); G01R 31/31708 (2013.01);
Abstract

A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.


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