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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11706949 B1

PDFFull Text
Date of Patent:
Jul. 18, 2023

Filed:

Mar. 04, 2021

Display device and method of manufacturing the same

Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Jong Oh Seo, Seoul, KR;

Byung Soo So, Yongin-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin-si, KR;

Attorney:

Kile Park Reed & Houtteman PLLC

Primary Examiner:

Dzung Tran

Int. Cl.
CPC ...
H01L 27/32 (2006.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01); H10K 71/00 (2023.01); G09G 3/3266 (2016.01); G09G 3/3275 (2016.01); G09G 3/3225 (2016.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H10K 59/12 (2023.01);
U.S. Cl.
CPC ...
H10K 59/1213 (2023.02); H10K 59/131 (2023.02); H10K 71/00 (2023.02); G09G 3/3225 (2013.01); G09G 3/3266 (2013.01); G09G 3/3275 (2013.01); G09G 2300/0426 (2013.01); H01L 27/1222 (2013.01); H01L 27/1274 (2013.01); H01L 29/66757 (2013.01); H01L 29/78615 (2013.01); H01L 29/78675 (2013.01); H10K 59/1201 (2023.02);
Abstract

A display device and a method of manufacturing a display device are provided. A display device includes a lower conductive pattern disposed on a substrate, a lower insulating layer disposed on the lower conductive pattern, the lower insulating layer including a first lower insulating pattern including an overlapping region overlapping the lower conductive pattern, and a protruding region. The display device includes a semiconductor pattern disposed on the first lower insulating pattern and having a side surface, the side surface being aligned with a side surface of the first lower insulating pattern or disposed inward from the side surface of the first lower insulating pattern, a gate insulating layer disposed on the semiconductor pattern, a gate electrode disposed on the gate insulating layer, and an empty space disposed between the substrate and the protruding region of the first lower insulating pattern.

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